Conventionally, the charge pump used within a frequency synthesizer (PLL), includes a pair of current mirror device, which is in response to a trigger input by the incoming up or down pulse signal, source or sink a fixed magnitude of current into the loop filter. This charge pump is widely employed in all analog PLL implementations due to its linear characteristics and low noise performance. However, the performance of this charge pump is affected by a wide range of inherent nonlinearities, such as up-down current mismatch, charge injection, clock feedthrough, and require intricate layout to suppress the random mismatches between the large current mirror devices. In addition, the useable linear output voltage range is a subset of the total available range from ground (0V) to the supply potential (VDD) and is typically less than 70% of the VDD. Moreover, the cascoding implemented within the constant current branches further restricts the output voltage range and the minimum supply voltage that can be utilized.
Further to this, in a PLL environment, the current (or charge) mismatch arising from the charge pump (hereinafter referred to as “CP”) directly translates into a reference spur at the PLL output spectrum. Therefore, the conventional current mirror CP commonly employs a high-gain auxiliary feedback loop to obtain precise matching of the UP-DN current magnitude. An example of such implementation is shown in FIG. 1 (Prior Art-1). As seen from FIG. 1, this implementation requires a rail-to-rail input/output range amplifier and comprises of replica bias paths that remain turned on, even when CP is in idle state (no UP or DN pulse input provided to the CP). Therefore, the state-of-the-art current-mirror CP implementation results in significantly increased complexity, power and area utilization.
In order to effectively suppress CP nonlinearities, a charge-based charge pump is proposed in Schober et al. [U.S. Pat. No. 8,525,564B2]. As indicated in FIG. 2 (Prior Art-2), the charge from pump capacitor, nominally charged to VDD, is shared to the load capacitor, following the trigger input by the incoming UP/DN pulse inputs. This capacitive charge re-distribution scheme results in improved matching performance and lower power consumption. However, due to the involved capacitive charge-sharing the useable linear range is even lower than the former case.
In this patent a novel charge-based charge pump architecture is proposed. The proposed CP retains all the merits of earlier charge-based charge pump, while extending the output voltage range from −0.84·VDD to 1.82·VDD. The approximated linear output voltage range also extends from ˜−0.7·VDD to ˜1.4·VDD. Such wide output voltage range can be utilized for wide tuning-range voltage-controlled oscillator (VCO)/PLL implementations. In addition, the steady-state ripple magnitude is less than 0.03% of its saturated output at −0.84·VDD/1.82·VDD, and the CP response is free from any memory effect. Thus, the proposed design can be employed for multiple applications, such as RF-Antenna switches, that can exploit the negative or higher-than-supply positive potential output from the CP.